Using make and writing Makefile ( in C++ or C )

makefile missing separator
This is a topic that many people are looking for. is a channel providing useful information about learning, life, digital marketing and online courses …. it will help you have an overview and solid multi-faceted knowledge . Today, would like to introduce to you Using make and writing Makefile ( in C++ or C ). Following along are instructions in the video below:

hello guys in this video Im going to show you how you can create and make make files in C or C++ in this test case Im using C++ to show you the demonstration on make files but the same rule you can apply in C programming also ok so to start with I have 4 files which are in C++ I have a main dot cpp function 1 dot cpp position 2 dot cpp and functions dot H so the mains dot CPP let me show you what I have in the main dot CPP so Im executing the function 1 and function 2 in my main dot CPP and the dependency is functions dot H which have the Declaration of both function 1 and function – okay so it doesnt matter whatever you program you have you just need to make the make file this is your requirement for example so why first of all we can you why should we use make file I believe when we have this make file and its in the folder sample we can just go to this sample folder and we can just give this command g+ + main dot cpp a function one dot cpp function two dot cpp and we want to make the executable file called hello and when we give this command it will create us this executable file right this is a simple GCC command but for example you have 50 or 100 header files and CPP files you cannot write all the CPP file name and add header file names and all the dependency and whatever you need it becomes tedious to compile your program if you have to do it with your hands so thats why we use make file so make file we use to reduce the compilation time and because whatever files are already compiled and they are not changed the make file detects them and if they make file doesnt execute the already compiled file it only executes the files which need compilations right or which have been changed so thats why so lets make a simple make file I have in the same folder I will create a simple make file I right click and create a new document empty document and I will name it as make file and just see here make file how I have spelled this make file with the capital M so it is the common convention to start make file with capital M then all the letters are small so just write this and Im going to open this make file here okay and in here I can write a target so I will write for example all and then I will press ENTER and I will just copy the same command which I have used to compile my program and paste it here but common convention in this execution of command and target this is a target you need to give a tab in

order to execute the command so after the target you need to give this tab to detect that its a command okay and I will save this make file here okay and by default menu alright this command make here it will detect the first target and it will execute the first target so for example if you have two targets compile and I dont have anything in compiled for example then by default it will execute all because its the first target and not compiled right and so let me show you the demonstration first so Im in the sample file and for example I have already created my make mine and I will right here make it will detect that first target is all and it will execute this command so I mean enter and you see here first command is executed and my executable file is made okay and for example your compile you your command is in the second target which is compile then how you can compile this or how you can give the make file command you just need to give make and then compiled because we need to execute the second target and by default it detects the first target right so this will also produce the same result when you execute it you see here it executed the same command right so this is about the commands okay and in make file you can also give comment by this hash so you can give this target when compiled all the files okay so like this you can provide commands to remember what or to see that what this target is made for so you can give command starting with this hash sign ok but we can see that thats this is doing the same thing this is executing the same command in here I have just copied and pasted this command and makes file can do more than that so for example I will give you the other example I will just delete this all the code I have written and I will just write this make file commands so I will explain you what I have written here first of all here let me explain you from here first so I have created three objects because I have three CPP files right and so these this is a target main dot o function one dot o and function two dot o is the target and the dependency so whatever you write after this : and with the space its the dependency its called the dependency so main dot o has the dependency main dot CPP which we have in our program write that main dot CPP this here so and one when you call main dot o it will execute this command G + + – C – C stands for compile and it will compile main dot CPP and it will check first whether it fulfils the dependency or our requirement

of main dot CPP so it should have main dot CPP first because it depends upon our command demands upon this okay so this is called dependency this is called target and this is called command okay in the same way I have created the object of function one and function to which have the dependency function to has dependency function dot two dot CPP and Im executing the function two dot CPP here and function one dot CPP here okay and the clean command I have given to clean all the object file and to clean or remove all the executable file so when I execute make clean it should remove all these object file and the executable file it has made now we come to this part hello and what this is doing is it is executing all our object files which we have created right so it has the dependency main dot o function dot o and function two dot o which we have created here okay and then it will execute or the command G plus plus so it will execute main dot o function one dot o function two dot o and we are creating the executable file hello from it right and then we call this target in our all targets when we write make all then our program is executed executed so it will go here first and it will see that we have to make this and the dependency of this is these three files then it will execute these three and then it will execute this command and create this executable file right so lets save this and lets compile it so I will right make all if you right make all then also it will go to first target because this first target name is me call or you can give the command make also because it will by a default go to the first target right so right now I will show you this by make all and press enter and you see here first it has gone to compile main dot CPP so it goes here because all depends upon hello and hello depends upon main dot oh so main dot Oh will be compiled first our main dot Oh will be executed first and it depends upon main dot CPP so this will be compiled first right then our function one will be compiled and then our function two dot CPP will be compiled and then it will create the result and it will show us the result now I have shown you I want to show you what this clean does right so its just a remove command of this object file star object or hello which is our executable file name right so I will just more Im just want to show the folder and see here what happens when I execute make clean so when I execute make clean see here when I have executed

may call it has created main dot o function to dot o and function one dot o right because we have our dependency in here and when I click or when I type make clean and press ENTER it will clean all our program and it will remove all the object file and executable file from here and once again when I make all when I give this command it creates object file and executable file once again right but still you can further improve this by declaring objects so how can we do this so lets make this make file more modular so I will just remove all this first or lets let it be there we will comment it and I will just paste this code here and just remove this okay so and makefile we can declare variables also and variables are declared like this so I will say the comment declare the variable and variable you can name it according to you but make file has some conventions so just I will show you where you can read about make file because make file is very broad topic and Im showing you just a basic things okay so you can declare variables like this CC is G plus plus so this is our compound type of compiler we are using and we can set the variables so this is a variable and this is a variable and so in this we are telling that which types CC will come the variable CC will contain which type of compiler we are using we can change it to GCC also if you are if you have a C program and in C flag we are giving the option which type of compiler option we want to give so minus c is for compilation – wall is for giving the warning so if you declare this kind of variable then you dont need to change for example we are using the CC here so whenever you want to change this g + + you dont need to change G + + here here here here you just change this variable CC here to GCC and this will be implemented here so thats why we declare variables so we have CC variable and C flag variables and this program or this code is the same as old which I have already mentioned and how you can call these variables here by giving this dollar sign and in the bracket just call the variables right so what I have done is I have just ripped last g+ + with this one right so lets see if I can show you the last code so you can see here in the last code which i have mentioned you cheese + + s here and I have only replaced the g + + with dollar and bracket and this Im calling this C C variable here in the same way Im calling wherever I

minus C I have included one more options – wall and this will also have had become tedious if you have to include this warning command – every function and by declaring variable it has become really easy you just need to add this warning come on here and it will be executed here also so you can call variables like this dollar and in the bracket you need to give the call to your variable soon I have replaced this like this and this will also execute the same comma same the same type of compilation but this has made our compilation more modular and this will come handy when you have hundreds of files right and I will save this make file and once again when I do make all so it says nothing to be made because I havent changed anything in my main main dot cpp or any of the files so suppose for example I just change my main dot cpp only one file and I will say just print some some message here by double quotes that theres is whatever any message and this is just to show you that when I change this only one file then what happens okay so once again I have saved this main file and I have changed it its change this file only and I havent changed function dot H or function one dot CPP or function two dot CPP or and earlier what was happening only all three files were compiling right and now I have changed the main file and I have executed this make all I will execute this command once again and you see here only one file only one command is executed which is main dot CPP and because we havent changed function one dot CPP and function two dot CPP the state of those two files will remain same and whatever file we have changed only this command will be executed so this will make our compilation faster okay so thats why we can use make files also so this is some of the basics I have shown you how to use make file and how you can create make files but make file is a big topic and you need to read me to create very modular make files so where you can read about make files just go to gnu dot o-r-g and so w w w GN u dot o-r-g just go to this site and this in here in the search just search for make while and press enter and you can see this second option g and you make and all the documentation of make file and make you can find it here okay so whenever you have time just give some time to read about make file and you will learn how to make very good make files from here okay I hope you have enjoyed this video please rate comment and subscribe and bye for now

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